Search - uart VHDL

[Com Port] 71477212NiosII_uart

Description: 串口sopc uart实现串口功能，包含帧的开始字节，命令字节-Serial sopc uart serial implementation features, including frame start byte, command byte
Platform: | Size: 4096 | Author: awublack | Hits:

[Industry research] UART_DESIGN

Description: The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
Platform: | Size: 141312 | Author: ltrko9kd | Hits:

[VHDL-FPGA-Verilog] UART

Description: UART通信协议的硬件描述语言代码，用与FPGA的总线接口开发-UART communication protocol of the hardware description language code, using the bus interface with the FPGA development
Platform: | Size: 22528 | Author: shigengxin | Hits:

[Embeded-SCM Develop] RS232.VHDL

Description: RS232 Communication function in VHDL for Spartan 3E
Platform: | Size: 1024 | Author: Tony Tan | Hits:

[VHDL-FPGA-Verilog] uart_ise_vhdl

Description: fpga里实现 uart 经典 vhdl语言写的 ise工程文件-fpga implementation in vhdl language classic uart of ise project file
Platform: | Size: 22528 | Author: 孙俪 | Hits:

[Linux-Unix] first_cpu

Description: nios ii cpu核，包含通用IO口、sdram、flash、uart-nios ii cpu、genernal io port、sdram、falsh、uart
Platform: | Size: 13319168 | Author: 陆yong | Hits:

[VHDL-FPGA-Verilog] UART

Description: UART是一种广泛应用于短距离、低速、低成本通信的串行传输接口.由于常用UART芯片比较复杂且移植性差,提出一种采用可编程器件FPGA实现UART的方法, 实现了对UART的模块化设计.首先简要介绍UART的基本特点,然后依据其系统组成设计顶层模块,再采用有限状态机设计接收器模块和发送器模块,所有功能的实现全部采用VHDL进行描述,并用Modelsim软件对所有模块仿真实现.最后将UART的核心功能集成到FPGA上,使整体设计紧凑,小巧,实现的UART功能稳定、可靠. -UART is a widely used short-range, low-speed, low-cost serial transmission interface communication. Because of the complexity of common UART chip and poor transplant, using a programmable FPGA devices to achieve UART way of the realization of the UART modular design. First of all, a brief introduction of the basic characteristics of UART, and then according to their top-level module system design, and then the design of finite state machine receiver module and transmitter module, the realization of all the features to describe the use of VHDL and Modelsim software used Simulation of all modules. Finally, the UART core functionality into the FPGA, so that the overall design of compact, compact, the UART function of the realization of stable and reliable.
Platform: | Size: 38912 | Author: 徐明宝 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于FPGA的uart源代码，异步串行通信，vhdl书写的。-uart codes。write with vhdl.
Platform: | Size: 280576 | Author: 陈 | Hits:

[VHDL-FPGA-Verilog] uart_receiver

Description: This UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.-This is UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.
Platform: | Size: 1024 | Author: bhagwan | Hits:

[VHDL-FPGA-Verilog] UART

Description: Hardware Design with VHDL Design Example: UART
Platform: | Size: 54272 | Author: j | Hits:

[VHDL-FPGA-Verilog] uart_vhdl

Description: 串口通讯的VHDL源码，波特率可自行设置，验证通过。-UART VHDL
Platform: | Size: 5120 | Author: 陈家钧 | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart send resive module
Platform: | Size: 1024 | Author: rez | Hits:

[OS Develop] UART

Description: A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.-A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.
Platform: | Size: 2048 | Author: Viral | Hits:

[Driver Develop] CameraDriver

Description: This module use OV7620 digital camera on the 24-bit RBG (8:8:8) data and display that in RS232 uart interface
Platform: | Size: 5120 | Author: Joelmir J Lopes | Hits:

[VHDL-FPGA-Verilog] FPGA_VHDL_code

Description: FPGA学习非常珍贵的资料，包括USB、UART、I2C、Ethernet、VGA、CAN等总线的VHDL实现，可以直接应用于实际项目中。需要的请下载。 -FPGA to learn very valuable information, including USB, UART, I2C, Ethernet, VGA, CAN bus, such as VHDL to achieve, can be directly applied to actual projects. Need to download.
Platform: | Size: 1605632 | Author: suzhenwei | Hits:

[Com Port] uart_module

Description: 实现精简的uart串口,格式起始位+8bit数据位+可配置的奇偶校验位+停止位-implement a smart UART interface
Platform: | Size: 4096 | Author: hut | Hits:

[VHDL-FPGA-Verilog] miniuart.tar

Description: 用VHDL描述的简单UART接口，能正确实现简单的功能-VHDL description with a simple UART interface
Platform: | Size: 6144 | Author: elvis | Hits:

[VHDL-FPGA-Verilog] nios_uart

Description: nios uart 在开发板上试过的，修改了，希望能有用-nios uart board tried in the development of
Platform: | Size: 3503104 | Author: mumu | Hits:

[Other] uart

Description: fpga内嵌入双向串行通讯口传输波特率可变可通过查询方式确定发送接收状态内置256字节发送接收缓冲区 -serial communication
Platform: | Size: 5120 | Author: tianzhijun | Hits:

[Com Port] UARTcode

Description: 串口UART通用异步接收/发送器的VHDL 源代码-Serial UART code
Platform: | Size: 17408 | Author: liuyinqiang | Hits:

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[Com Port] 71477212NiosII_uart

[Industry research] UART_DESIGN

[VHDL-FPGA-Verilog] UART

[Embeded-SCM Develop] RS232.VHDL

[VHDL-FPGA-Verilog] uart_ise_vhdl

[Linux-Unix] first_cpu

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart_receiver

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart_vhdl

[VHDL-FPGA-Verilog] uart

[OS Develop] UART

[Driver Develop] CameraDriver

[VHDL-FPGA-Verilog] FPGA_VHDL_code

[Com Port] uart_module

[VHDL-FPGA-Verilog] miniuart.tar

[VHDL-FPGA-Verilog] nios_uart

[Other] uart

[Com Port] UARTcode

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